// (C) Copyright 2012 Enlightv. All rights reserved.

`timescale 1ns/100ps

module reset_sync 
#(parameter
    DFF_NUM = 2
)
(
    input  I_clk,
    input  I_reset_in,
    output O_reset_out
);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
(* ASYNC_REG = "TRUE" *) reg  [ DFF_NUM - 1: 0] dff;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_clk or negedge I_reset_in)
    if (!I_reset_in)
        begin
        dff <= {DFF_NUM{1'b0}};
        end
    else
        begin
        dff[0] <= 1'b1;
        dff[DFF_NUM-1:1] <= dff[DFF_NUM-2:0];
        end

assign O_reset_out = dff[DFF_NUM-1];

endmodule

